The present disclosure relates to processor verification in general, and to checking of a simulated execution of a processor for correct execution of transactions, in particular.
Computerized devices control almost every aspect of our life from writing documents to controlling traffic lights. However, computerized devices are bug-prone, and thus require a testing phase in which the bugs should be discovered. The testing phase is considered one of the most difficult tasks in designing a computerized device.
The cost of a bug may be enormous, as its consequences may be disastrous. For example, a bug may cause the injury of a person relying on the designated behavior of the computerized device. Additionally, a bug in hardware or firmware may be expensive to fix, as patching it requires call-back of the computerized device. Hence, many developers of computerized devices invest a substantial portion, such as 70%, of the development cycle to discover erroneous behaviors of the computerized device.
Correctness of a functionality of a processor, or similar electronic circuit or computing device, may be verified. The verification process may be performed based upon a description of the processor, such as provided using a descriptive language such as for example VHDL, Verilog, SystemC or the like. In order to verify the processor, a test program may be generated by a test generator and a simulator, configured to simulate an execution of the processor, also referred to as the target processor, based on the functionality described using the descriptive language, in respect to the test program. Correctness of the simulated execution may be checked in order to detect bugs in the processor. In some cases, several test programs may be generated. Each test program may be executed more than once.
Some processor design includes support for transactional memory model. A transaction is a construct in the machine language that can be used by parallel applications when a number of processes access a shared resource. Instructions of a transaction appear to be performed atomically. The instructions, performed by a processing entity of the processor, such as a hardware thread, a core or the like, are performed without any observable collisions with any memory access performed by other processing entities.
Some processors further require a serializability property of the transactions. The serializability property requires that an order between transactions be the same for all processing entities of the processor. In some exemplary embodiments, in case a first order between transactions, as observed by a first processing entity of the processor, is different than a second order between transactions, as observed by a second processing entity of the processor, the processor may be considered as not holding the serializability property.